###############################################################################
# Copyright (c) 2013, 2018 Potential Ventures Ltd
# Copyright (c) 2013 SolarFlare Communications Inc
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#
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# modification, are permitted provided that the following conditions are met:
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#       names of its contributors may be used to endorse or promote products
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###############################################################################

TOPLEVEL_LANG ?= verilog

TOPLEVEL := sample_module

PWD=$(shell pwd)

COCOTB?=$(PWD)/../../..

ifeq ($(TOPLEVEL_LANG),verilog)
    VERILOG_SOURCES = $(COCOTB)/tests/designs/sample_module/sample_module.sv
else ifeq ($(TOPLEVEL_LANG),vhdl)
    VHDL_SOURCES =  $(COCOTB)/tests/designs/sample_module/sample_module_pack.vhdl $(COCOTB)/tests/designs/sample_module/sample_module_1.vhdl $(COCOTB)/tests/designs/sample_module/sample_module.vhdl

    ifneq ($(filter $(SIM),ius xcelium),)
        SIM_ARGS += -v93
    endif
else
    $(error "A valid value (verilog or vhdl) was not provided for TOPLEVEL_LANG=$(TOPLEVEL_LANG)")
endif

include $(shell cocotb-config --makefiles)/Makefile.sim
